IDE 40-pin Pinout
Parallel ATA (PATA) 40-pin ribbon-cable interface for hard drives and optical drives.
Overview
The 40-pin IDE/PATA connector is the classic dual-row header (two rows of 20 on 2.54 mm pitch) used by parallel ATA drives. It carries a 16-bit data bus, three address lines, ATA read/write strobes, DMA handshaking and control signals.
Pin 20 is the keying position (removed). The later 80-conductor cable keeps the same 40-pin connector but interleaves a ground between every signal for UDMA, with pin 34 used to detect the 80-conductor cable.
Pinout
| Pin | Name | Function | Description |
|---|---|---|---|
| 1 | -RESET | SIGNAL | Drive reset, active low |
| 2 | GND | GND | Ground |
| 3 | DD7 | DATA | Data bus bit 7 |
| 4 | DD8 | DATA | Data bus bit 8 |
| 5 | DD6 | DATA | Data bus bit 6 |
| 6 | DD9 | DATA | Data bus bit 9 |
| 7 | DD5 | DATA | Data bus bit 5 |
| 8 | DD10 | DATA | Data bus bit 10 |
| 9 | DD4 | DATA | Data bus bit 4 |
| 10 | DD11 | DATA | Data bus bit 11 |
| 11 | DD3 | DATA | Data bus bit 3 |
| 12 | DD12 | DATA | Data bus bit 12 |
| 13 | DD2 | DATA | Data bus bit 2 |
| 14 | DD13 | DATA | Data bus bit 13 |
| 15 | DD1 | DATA | Data bus bit 1 |
| 16 | DD14 | DATA | Data bus bit 14 |
| 17 | DD0 | DATA | Data bus bit 0 |
| 18 | DD15 | DATA | Data bus bit 15 |
| 19 | GND | GND | Ground |
| 20 | KEY | SIGNAL | Keying position (pin removed) |
| 21 | DMARQ | SIGNAL | DMA request |
| 22 | GND | GND | Ground |
| 23 | -DIOW / STOP | SIGNAL | Write strobe (Ultra DMA: STOP) |
| 24 | GND | GND | Ground |
| 25 | -DIOR | SIGNAL | Read strobe / Ultra DMA ready |
| 26 | GND | GND | Ground |
| 27 | IORDY | SIGNAL | I/O channel ready / Ultra DMA ready |
| 28 | CSEL | VIDEO | Cable select / spindle sync |
| 29 | -DMACK | SIGNAL | DMA acknowledge |
| 30 | GND | GND | Ground |
| 31 | INTRQ | SIGNAL | Interrupt request |
| 32 | -IOCS16 | SIGNAL | 16-bit I/O (obsolete in ATA-3+) |
| 33 | DA1 | SIGNAL | Address bit 1 |
| 34 | -PDIAG / CBLID | SIGNAL | Passed diagnostics / 80-conductor cable detect |
| 35 | DA0 | SIGNAL | Address bit 0 |
| 36 | DA2 | SIGNAL | Address bit 2 |
| 37 | -CS0 | SPI | Chip select for command-block registers |
| 38 | -CS1 | SPI | Chip select for control-block registers |
| 39 | -DASP | SIGNAL | Drive active / slave present (LED driver) |
| 40 | GND | GND | Ground |
Notes
- Pin 20 is keyed (no pin) for orientation.
- Some control pins take Ultra DMA dual functions.
- The 44-pin 2.5-inch variant adds power pins beyond these 40.
Reference: ATA/ATAPI (PATA) 40-pin interface pinout· verified 2026-06-27