ISP 10-pin (AVR) Pinout
The legacy AVR ISP programming header (2x5, 2.54mm) with interleaved grounds.
Overview
The older 10-pin AVR ISP header (STK200/STK500 standard) carries the same SPI programming signals as the 6-pin version but adds interleaved grounds for better ribbon-cable noise immunity. It is a 2x5 header on 0.1 inch pitch.
Modern tools ship the 6-pin header and treat the 10-pin as legacy (an adapter is needed).
Pinout
| Pin | Name | Function | Description |
|---|---|---|---|
| 1 | MOSI | SPI | Master-Out Slave-In (programmer to target) |
| 2 | VCC / VTG | POWER | Target supply / voltage reference |
| 3 | LED / NC | SIGNAL | Programmer status LED line (often unconnected) |
| 4 | GND | GND | Ground |
| 5 | RESET | SIGNAL | Target reset |
| 6 | GND | GND | Ground |
| 7 | SCK | SPI / CLK | SPI serial clock |
| 8 | GND | GND | Ground |
| 9 | MISO | SPI | Master-In Slave-Out (target to programmer) |
| 10 | GND | GND | Ground |
Notes
- Interleaved grounds (pins 4,6,8,10) improve ribbon-cable noise immunity.
- Do not confuse with the AVR JTAG 10-pin or ARM Cortex 10-pin (different pinouts).
Reference: Kanda AVR ISP circuit schematics / Batsocks· verified 2026-06-27