JTAG 20-pin (ARM) Pinout
The legacy ARM-20 JTAG/SWD debug header (2x10, 2.54mm).
Overview
The 20-pin ARM JTAG header (ARM-20) is the legacy 0.1 inch debug connector for ARM cores, carrying full JTAG (TDI/TDO/TMS/TCK/nTRST) or SWD (SWDIO/SWCLK on the TMS/TCK pins). All even pins are ground.
For modern Cortex-M SWD targets only VTref, SWDIO (7), SWCLK (9), SWO (13), nRESET (15) and a ground are used; the JTAG-only pins are legacy.
Pinout
| Pin | Name | Function | Description |
|---|---|---|---|
| 1 | VTref | POWER | Target I/O voltage reference (probe input) |
| 2 | VCC / Vsupply | POWER | Often NC; some probes supply power here |
| 3 | nTRST | SIGNAL | JTAG TAP reset (active low) |
| 4 | GND | GND | Ground |
| 5 | TDI | PAIR / DATA | Test Data In (probe to target) |
| 6 | GND | GND | Ground |
| 7 | TMS / SWDIO | PAIR / DATA | Test Mode Select / SWD data |
| 8 | GND | GND | Ground |
| 9 | TCK / SWCLK | PAIR / CLK | Test Clock / SWD clock |
| 10 | GND | GND | Ground |
| 11 | RTCK | GND / CLK | Return Test Clock (adaptive clocking) |
| 12 | GND | GND | Ground |
| 13 | TDO / SWO | PAIR / DATA | Test Data Out / Serial Wire Output |
| 14 | GND | GND | Ground |
| 15 | nRESET | SIGNAL | Target system reset (active low) |
| 16 | GND | GND | Ground |
| 17 | DBGRQ / NC | SIGNAL | Debug Request (mostly unused) |
| 18 | GND | GND | Ground |
| 19 | DBGACK / NC | SIGNAL | Debug Acknowledge (mostly unused; 5V on some J-Links) |
| 20 | GND | GND | Ground |
Notes
- All even pins 4-20 are ground in the base ARM-20 spec; some probes repurpose pin 2/19.
- For SWD only VTref, pins 7, 9, 13, 15 plus a ground are needed.
Reference: Lauterbach ARM JTAG Interface Specifications (ARM-20)· verified 2026-06-27