JTAG / SWD (ARM Cortex Debug) Header Pinout
The ARM 10-pin Cortex debug header — SWD (2-wire) and full JTAG signals.
Overview
ARM Cortex chips are debugged over either SWD (Serial Wire Debug, 2 signals: SWDIO + SWCLK) or full JTAG (TMS/TCK/TDI/TDO). The standard 0.05" 10-pin Cortex Debug header carries both — SWD reuses the TMS/TCK pins, so the same header works for either.
At minimum a debugger needs SWDIO, SWCLK, GND, and VTREF (to sense target voltage); nRESET and SWO (trace output) are recommended.
Pinout
| Pin | Name | Function | Description |
|---|---|---|---|
| 1 | VTREF | POWER | Target reference voltage (sense, not supply). |
| 2 | SWDIO / TMS | DATA | SWD data / JTAG mode select. |
| 3 | GND | GND | Ground. |
| 4 | SWCLK / TCK | CLK | SWD/JTAG clock. |
| 5 | GND | GND | Ground. |
| 6 | SWO / TDO | DATA | Trace output / JTAG data out. |
| 7 | KEY | Keyed (pin removed). | |
| 8 | TDI | DATA | JTAG data in (unused in SWD). |
| 9 | GNDDetect | GND | Ground / cable detect. |
| 10 | nRESET | GPIO | Target reset (active low). |
Notes
- SWD needs only SWDIO (2), SWCLK (4), GND, and VTREF (1); add nRESET (10) and SWO (6) if you can.
- The legacy 20-pin 0.1" JTAG header carries the same logical signals with more grounds.
Reference: ARM Cortex Debug Connector· verified 2026-06-21