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74F112 Dual JK Flip-Flop
74F112
Texas Instrumentsic logic
The SN74F112 is a dual negative-edge-triggered J-K flip-flop with clear and preset functions, designed for digital logic applications.
In stock
Specifications
4- Operating Voltage
- 4.5 V to 5.5 V
- Supply Current
- 12 mA to 19 mA
- Temperature Range
- 0°C to 70°C
- Package
- SOIC, PDIP, SOP
Pinout
16| Pin | Name | Functions | Notes |
|---|---|---|---|
| 1 | CLK1 | GPIO | Clock input for the first flip-flop. |
| 2 | K1 | GPIO | Input for the second state of the J-K flip-flop in the first flip-flop. |
| 3 | J1 | GPIO | Input for the first state of the J-K flip-flop in the first flip-flop. |
| 4 | PRE1 | GPIO | Preset input for the first flip-flop. |
| 5 | CLR1 | GPIO | Clear input for the first flip-flop. |
| 6 | Q1 | GPIO | Output of the first flip-flop. |
| 7 | Q1' | GPIO | Complementary output of the first flip-flop. |
| 8 | GND | GND | Ground reference. |
| 9 | CLK2 | GPIO | Clock input for the second flip-flop. |
| 10 | K2 | GPIO | Input for the second state of the J-K flip-flop in the second flip-flop. |
| 11 | J2 | GPIO | Input for the first state of the J-K flip-flop in the second flip-flop. |
| 12 | PRE2 | GPIO | Preset input for the second flip-flop. |
| 13 | CLR2 | GPIO | Clear input for the second flip-flop. |
| 14 | Q2 | GPIO | Output of the second flip-flop. |
| 15 | Q2' | GPIO | Complementary output of the second flip-flop. |
| 16 | VCC | POWER | Supply voltage input. |
Interactive pinout
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74F112
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