← All parts
74HCT112 Dual JK Flip-Flop
74HCT112
Nexperiaic logic
The 74HCT112 is a dual negative-edge triggered JK flip-flop designed for use in digital circuits, featuring asynchronous set and reset inputs.
In stock
Specifications
4- Operating Voltage
- 2.0 to 6.0 V
- Supply Current
- 50 mA max
- Temperature Range
- -40 °C to +125 °C
- Package
- SO16, TSSOP16
Pinout
16| Pin | Name | Functions | Notes |
|---|---|---|---|
| 1CP | clock input (HIGH-to-LOW; edge-triggered) | GPIO | |
| 2CP | clock input (HIGH-to-LOW; edge-triggered) | GPIO | |
| 1K | data input | GPIO | |
| 2K | data input | GPIO | |
| 1J | data input | GPIO | |
| 2J | data input | GPIO | |
| 1SD | set input (active LOW) | GPIO | |
| 2SD | set input (active LOW) | GPIO | |
| 1Q | true flip-flop output | GPIO | |
| 2Q | true flip-flop output | GPIO | |
| 1Q | complement flip-flop output | GPIO | |
| 2Q | complement flip-flop output | GPIO | |
| 1RD | reset input (active LOW) | GPIO | |
| 2RD | reset input (active LOW) | GPIO | |
| VCC | supply voltage | POWER | |
| GND | ground (0 V) | GND |
Interactive pinout
Highlight:
74HCT112
Click a pin to copy its name · tap a tag above to spotlight a bus.