← All parts
74LS240 Octal Buffer (inv)
74LS240
Texas Instrumentsic logic
The 74LS240 Octal Buffer (inv) is a logic buffer that inverts its input signal and can be used to drive bus lines or memory address registers.
In stock
Specifications
3- Operating Voltage
- 7 V (MAX) / 5.5 V (MIN) V
- Supply Current
- 27 mA (Outputs high, All) mA
- Package
- DB (SSOP), DW (SOIC), J (CDIP), N (PDIP), NS (SOP), FK (LCCC)
Pinout
20| Pin | Name | Functions | Notes |
|---|---|---|---|
| 1 | 1G | GPIO | Channel 1 output enable |
| 2 | 1A1 | GPIO | Channel 1, A side 1 |
| 3 | 2Y4 | GPIO | Channel 2, Y side 4 |
| 4 | 1A2 | GPIO | Channel 1, A side 2 |
| 5 | 2Y3 | GPIO | Channel 2, Y side 3 |
| 6 | 1A3 | GPIO | Channel 1, A side 3 |
| 7 | 2Y2 | GPIO | Channel 2, Y side 2 |
| 8 | 1A4 | GPIO | Channel 1, A side 4 |
| 9 | 2Y1 | GPIO | Channel 2, Y side 1 |
| 10 | GND | GND | Ground |
| 11 | 2A1 | GPIO | Channel 2, A side 1 |
| 12 | 1Y4 | GPIO | Channel 1, Y side 4 |
| 13 | 2A2 | GPIO | Channel 2, A side 2 |
| 14 | 1Y3 | GPIO | Channel 1, Y side 3 |
| 15 | 2A3 | GPIO | Channel 2, A side 3 |
| 16 | 1Y2 | GPIO | Channel 1, Y side 2 |
| 17 | 2A4 | GPIO | Channel 2, A side 4 |
| 18 | 1Y1 | GPIO | Channel 1, Y side 1 |
| 19 | 2G/2G | GPIO | Channel 2 output enable |
| 20 | VCC | POWER | Power supply |
Interactive pinout
Highlight:
74LS240
Click a pin to copy its name · tap a tag above to spotlight a bus.