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74LVC112 Dual JK Flip-Flop
74LVC112
Texas Instrumentsic logic
A dual negative-edge-triggered J-K flip-flop designed for 1.65V to 3.6V operation, used for data retention and latching in bus interface applications.
In stock
Specifications
8- Operating Voltage
- 1.65V to 3.6V
- Supply Current
- 10μA (inactive) at VCC = 3.3V, TA = 25°C
- Interface
- CMOS
- Resolution
- N/A
- Range
- N/A
- Accuracy
- N/A
- Temperature Range
- -40°C to +125°C
- Package
- DB (SSOP, 16), PW (TSSOP, 16), DGV (TVSOP, 16), NS (SOP, 16), D (SOIC, 16)
Pinout
16| Pin | Name | Functions | Notes |
|---|---|---|---|
| 1 | 1CLK | GPIO | Clock input |
| 2 | 1K | GPIO | J-K flip-flop K input |
| 3 | 1J | GPIO | J-K flip-flop J input |
| 4 | 1PRE | GPIO | Preset input, sets Q high and Q low on power-up |
| 5 | 1Q | GPIO | Output of the first flip-flop |
| 6 | 1Q | GPIO | Complementary output of the first flip-flop |
| 7 | 2Q | GPIO | Output of the second flip-flop |
| 8 | GND | GND | Ground pin |
| 9 | 2Q | GPIO | Complementary output of the second flip-flop |
| 10 | 2PRE | GPIO | Preset input, sets Q high and Q low on power-up for the second flip-flop |
| 11 | 2J | GPIO | J-K flip-flop J input for the second flip-flop |
| 12 | 2K | GPIO | J-K flip-flop K input for the second flip-flop |
| 13 | 2CLK | GPIO | Clock input for the second flip-flop |
| 14 | 2CLR | GPIO | Clear input, sets Q low and Q high on power-up for the second flip-flop |
| 15 | 1CLR | GPIO | Clear input, sets Q low and Q high on power-up for the first flip-flop |
| 16 | VCC | POWER | Supply voltage pin |
Interactive pinout
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74LVC112
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